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STB80NF10
N-CHANNEL 100V - 0.012 - 80A D2PAK LOW GATE CHARGE STripFETTM POWER MOSFET
TYPE STB80NF10
s s s s
VDSS 100 V
RDS(on) < 0.015
ID 80 A
TYPICAL RDS(on) = 0.012 EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION
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D2PAK
DESCRIPTION This Power MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer application. It is also intended for any application with low gate charge drive requirements.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS s HIGH-EFFICIENCY DC-DC CONVERTERS s UPS AND MOTOR CONTROL
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID(*) ID IDM (q) PTOT dv/dt (1) EAS (2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 100 100 20 80 50 320 300 2 9 245 -65 to 175 175
(1) I SD 80A, di/dt 300A/s, VDD V (BR)DSS, Tj T JMAX. (2) Starting T j = 25C, I D = 80A, VDD = 50V
Unit V V V A A A W W/C V/ns mJ C C
(q) Pulse width limited by safe operating area (*) Limited by Package
February 2001
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THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.5 62.5 300 C/W C/W C
ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V Min. 100 1 10 100 Typ. Max. Unit V A A nA
ON (1)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10V, ID = 40 A Min. 2 Typ. 3 0.012 Max. 4 0.015 Unit V
DYNAMIC
Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID =40 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 20 4300 600 230 Max. Unit S pF pF pF
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ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 50V, ID = 40A RG = 4.7 VGS = 10V (see test circuit, Figure 3) VDD = 80V, ID = 80A, VGS = 10V Min. Typ. 40 145 140 23 51 189 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol td(off) Parameter Turn-off-Delay Time Test Conditions VDD = 50V, ID = 40A, RG = 4.7, VGS = 10V (see test circuit, Figure 3) Vclamp =80V, ID =80A RG = 4.7, VGS = 10V (see test circuit, Figure 5) Min. Typ. 134 Max. Unit ns
tf td(off) tf tc Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM
Fall Time Off-voltage Rise Time Fall Time Cross-over Time Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 80A, VGS = 0 ISD = 80A, di/dt = 100A/s, VDD = 50V, Tj = 150C (see test circuit, Figure 5) Test Conditions Min.
115 111 125 185 Typ. Max. 80 320 1.3 155
ns ns ns ns Unit A A V ns
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedence
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Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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D2PAK MECHANICAL DATA
mm. DIM. MIN. A A1 A2 B B2 C C2 D D1 E E1 G L L2 L3 M R V2 0 4.88 15 1.27 1.4 2.4 0.4 8 10 8.5 5.28 15.85 1.4 1.75 3.2 0.192 0.590 0.050 0.055 0.094 0.015 4.4 2.49 0.03 0.7 1.14 0.45 1.23 8.95 8 10.4 0.393 0.334 0.208 0.625 0.055 0.068 0.126 TYP MAX. 4.6 2.69 0.23 0.93 1.7 0.6 1.36 9.35 MIN. 0.173 0.098 0.001 0.027 0.044 0.017 0.048 0.352 0.315 TYP. MAX. 0.181 0.106 0.009 0.036 0.067 0.023 0.053 0.368 inch
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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